A well known problem in the art of read only memories is that the circuitry required to access, i.e., to address and read the memory, requires area on the memory chip, because the memory cells are read using decoders and selectors located on the periphery of the memory array. According to the prior art, the more dense the memory array, the more area required for the decoders and selectors relative to the memory array area. As a result, for a very high density memory array, such as is disclosed in U.S. patent application Ser. No. 08/748,035, now U.S. Pat. No. 5,847,442 which is assigned to the same assignee as the present invention and is incorporated by reference as if set forth fully herein, it is impractical to use prior art access techniques, because the area overhead required for the decoders and selectors essentially negates the advantage of the increased memory density.